Lina Hope
Hangzhou, China – T-Head, Alibaba’s advanced chip subsidiary, today made a landmark announcement at the 2026 Apsara Conference in Hangzhou, unveiling its next-generation Zhenwu V900 AI chip. Designed for both high-performance training and inference workloads, the V900 represents a significant leap in T-Head’s AI accelerator capabilities. Concurrently, the company provided a detailed roadmap for its future Yitian server CPUs, underscoring a strategic pivot towards a comprehensive, full-stack chip strategy encompassing computing, storage, and networking. This move reflects the increasing demands of burgeoning AI models and the widespread adoption of sophisticated agentic applications, which necessitate integrated hardware and software solutions.
The Apsara Conference, Alibaba’s flagship annual technology event, served as the ideal platform for these revelations. Historically a showcase for Alibaba Cloud’s innovations, the conference has evolved to highlight the foundational hardware underpinning its vast cloud infrastructure and AI ecosystem. T-Head’s announcements signify not just new product launches but a deeper commitment to designing integrated solutions tailored for the escalating complexity of artificial intelligence.
The Zhenwu V900: A New Benchmark in AI Acceleration
The Zhenwu V900 stands as T-Head’s latest high-end AI chip, engineered to tackle the most demanding AI computing workloads. Building upon the company’s proprietary parallel computing architecture, T-Head claims the V900 delivers a remarkable three times the performance of its predecessor, the Zhenwu M890, solidifying its position as the company’s most powerful in-house AI chip to date. This substantial performance uplift is critical for handling the exponentially growing computational requirements of contemporary large language models (LLMs) and advanced AI systems.
A key highlight of the V900 is its robust memory configuration and impressive inter-chip bandwidth. The chip is equipped with a substantial 216GB of high-bandwidth memory (HBM), a critical component for processing the massive datasets and model parameters characteristic of modern AI. This large memory capacity is designed to significantly reduce the overhead associated with model partitioning and data movement, which are common bottlenecks in large-scale AI training. Furthermore, the V900 boasts an inter-chip bandwidth of 1,200GB/s, facilitating rapid data exchange between multiple chips within a system. Such high bandwidth is crucial for efficient distributed training, where multiple accelerators collaborate on a single model.
In line with industry trends focusing on efficiency and cost reduction, the Zhenwu V900 natively supports low-precision computing formats, including FP8 and FP4. These formats allow for computations to be performed with fewer bits, leading to lower memory footprint, reduced power consumption, and faster processing speeds, particularly beneficial for AI inference at scale. For organizations deploying large AI models, the ability to leverage lower-precision computing translates directly into improved efficiency and reduced operational costs without a significant compromise in model accuracy for many applications. This feature is particularly relevant as AI models move from pure research to widespread commercial deployment, where inference efficiency becomes paramount.
From Accelerators to Integrated Systems: A Full-Stack Approach
A defining characteristic of the V900’s design philosophy is its integration into a larger system rather than functioning merely as a standalone accelerator. T-Head’s vision extends beyond individual chip performance, focusing on how these chips interact within a cohesive computing environment. To achieve this, T-Head utilizes its proprietary ICN Switch interconnect chips, which are central to forming "supernodes" by linking multiple V900 chips. This advanced interconnect technology provides native memory semantics and unified memory addressing, enabling seamless communication and resource sharing across thousands of AI chips with full-bandwidth interconnection.
T-Head articulated that this architecture allows more than 1,000 V900 chips to operate collectively as a single, unified system. This level of aggregation is specifically engineered to address the monumental challenges posed by training trillion-parameter models and satisfying the immense, concurrent inference demands generated by sophisticated AI agents. In such demanding workloads, simply increasing the number of AI accelerators is insufficient; the efficiency of communication between chips, coupled with seamless coordination across computing, storage, and networking components, becomes critically important. The ICN Switch is T-Head’s answer to these communication bottlenecks, ensuring data flows freely and efficiently across the entire AI cluster.
Demonstrating this integrated approach, Alibaba showcased a new-generation supernode server at the conference. This server seamlessly integrates the Zhenwu V900 AI chips, the ICN Switch interconnects, Panmai smart NICs (Network Interface Cards), and Zhenyue SSD controllers. This comprehensive system design brings computing, networking, and storage components together under a unified architecture, optimizing performance and reducing latency across the entire AI infrastructure stack. When combined with Alibaba Cloud’s newly designed AI computing center network architecture, T-Head claims that a single AI computing cluster utilizing these integrated chips can scale to an astonishing 500,000 accelerators. This immense scalability positions Alibaba Cloud to host and train some of the world’s largest and most complex AI models.
This strategic emphasis on system-level integration is not entirely new for T-Head. Supernode servers based on the previous-generation Zhenwu M890 have already achieved large-scale commercial deployment, successfully supporting models exceeding two trillion parameters, including Alibaba’s own Qwen3.8 and Kimi K3. The underlying capabilities and infrastructure derived from these deployments are also made accessible to developers through Alibaba Cloud’s Bailian platform, a testament to T-Head’s commitment to fostering a robust AI ecosystem. T-Head further stated that its Zhenwu series chips have served over 650 enterprise customers across a diverse range of sectors, including autonomous driving, finance, large language models, embodied AI, energy, and manufacturing, highlighting the versatility and real-world applicability of its AI solutions.
The Yitian Server CPU Roadmap: Powering the Core Infrastructure
Complementing its advancements in AI accelerators, T-Head also provided significant updates on the roadmap for its Yitian server CPUs. These CPUs are crucial for handling general-purpose computing tasks, data management, and orchestrating the vast AI workloads within Alibaba Cloud’s data centers. The roadmap, announced at the Apsara Conference, schedules the launch of the Yitian 720 and Yitian 730 in the third quarter of 2027.
The Yitian 720 is slated to bring substantial improvements focusing on single-core performance, core density, and energy efficiency. These enhancements are vital for cloud environments where optimizing resource utilization and minimizing power consumption directly impact operational costs and environmental sustainability. The Yitian 730, on the other hand, will leverage a new CPU microarchitecture developed entirely by T-Head. This proprietary design is projected to deliver up to 1.4 times the single-core SPECint2017/GHz performance compared to the preceding Yitian 710, indicating a significant boost in raw computational power for diverse server workloads. The Yitian 710, Alibaba’s first ARM-based server CPU, introduced in 2021, marked T-Head’s initial foray into high-performance server processors, and the subsequent generations aim to build aggressively on that foundation.
A particularly forward-looking aspect of the Yitian roadmap is the planned Yitian 750, which will natively support T-Head’s proprietary ICN inter-chip interconnect protocol. This crucial integration will enable the CPU to connect directly and seamlessly with Zhenwu AI chips. As AI server architectures become increasingly complex and heterogeneous, the need for closer coordination between CPUs and AI accelerators has shifted from a mere hardware assembly task to a fundamental aspect of system-level design. The ICN-enabled Yitian 750 will facilitate tighter coupling, lower latency, and higher bandwidth communication between the general-purpose CPU and specialized AI accelerators, thereby unlocking greater overall system performance and efficiency for integrated AI workloads.
Broader Impact and Strategic Implications
Taken together, T-Head’s comprehensive product roadmap, encompassing CPUs, AI accelerators, networking, and storage components, signals a profound strategic evolution. The emphasis has shifted from merely optimizing the performance of individual chips to orchestrating a sophisticated, interconnected ecosystem. This full-stack approach is a direct response to the broader paradigm shift in AI infrastructure, where bottlenecks are no longer confined solely to raw computational power. Instead, critical limitations frequently arise in areas such as chip-to-chip communication, memory capacity, network bandwidth, and efficient data access. T-Head’s strategy aims to address these multifaceted challenges holistically.
For Alibaba, these announcements are part of a broader, concerted effort to construct an end-to-end AI computing stack. By developing its own chips, networking solutions, storage systems, and the underlying software stack, Alibaba aims to reduce its reliance on external suppliers, gain greater control over its technological destiny, and optimize its cloud infrastructure for its vast internal AI operations and external cloud customers. This vertical integration is a powerful competitive advantage, allowing Alibaba Cloud to offer highly optimized and differentiated AI services. Alibaba Group CEO Wu Yongming underscored this ambition during the conference, expressing T-Head’s expectation for its annual AI chip shipments to increase significantly as its products achieve wider adoption across various industries.
On a national level, T-Head’s advancements hold significant implications for China’s burgeoning AI chip industry. The strategic move towards system-level infrastructure highlights a growing maturity within domestic chipmakers, who are increasingly looking to compete not just on raw accelerator performance but also on the critical interconnect, memory, and software layers that are essential for effectively running increasingly massive and complex AI models. In an era of geopolitical tensions and supply chain uncertainties, T-Head’s efforts contribute significantly to China’s drive for greater technological self-sufficiency and leadership in advanced semiconductor design.
During the Apsara Conference, T-Head also engaged the developer community by showcasing its full-stack chip solutions and hosting hands-on workshops centered around the T-Head SAIL software stack. These workshops covered crucial areas such as model training, inference optimization, and general software optimization, emphasizing the importance of a robust software ecosystem to unlock the full potential of its advanced hardware. This commitment to developers ensures that the innovative hardware can be effectively leveraged by a wide array of AI practitioners and enterprises.
The Zhenwu V900 is expected to enter mass production and become commercially available in the first quarter of 2027. With the Zhenwu V900 and the ambitious Yitian CPU roadmap, T-Head is not just launching new products; it is articulating a comprehensive, long-term vision for powering the future of AI, solidifying Alibaba’s position in the global AI infrastructure race, and significantly advancing China’s domestic chip capabilities.
Evan Lee Salim
Nana Muazin
